The present invention relates to a semiconductor integrated circuit such as a gate array or the like.
In a semiconductor integrated circuit, a clock has heretofore been used in general for synchronization of an internal operation. The clock is supplied to respective logic circuits or the like in the integrated circuit through clock drivers and clock conductive lines.
The respective clock drivers and respective circuit blocks are respectively supplied with a source potential and a ground potential by power and ground lines. In the present application, the power and ground lines are collectively called “power conductive line”.
As technologies related to the clock drivers and power conductive line, for example, the following Patent Documents have been known.
In a semiconductor integrated circuit disclosed in Japanese Patent Application Laid-Open No. Hei 7(1995)-240468, a power conductive line is formed in a lattice form and clock drivers are placed in the vicinity of the center thereof (see FIG. 1 of the same document). Here the power conductive line includes power branch lines disposed so as to intersect in all directions, and a power trunk line disposed along the outer periphery of the integrated circuit.
Even in a semiconductor integrated circuit disclosed in Japanese Patent Application Laid-Open No. 2001-7293, a power conductive line is formed in a lattice form in a manner similar to the above publication. Even in this example, the power conductive line has power branch lines placed so as to intersect in every direction, and a power trunk line disposed along the outer periphery of the integrated circuit. Clock drivers are disposed directly below the power trunk line.
In the semiconductor integrated circuit disclosed in each of the above publications, the clock drivers and circuit blocks make use of the same power conductive line. A region for forming each clock driver and a region for forming each logic circuit or the like are close to each other although not identical. Therefore, the conventional semiconductor integrated circuit is accompanied by a drawback that when noise is produced by the clock drivers, it is propagated to the logic circuits or the like through the power conductive line. This noise will lead to a malfunction of each logic circuit or the like.
While there is now an increasingly demand for speeding up of the operation of a semiconductor integrated circuit, there is a need to increase the frequency of a synchronizing clock for the purpose of enhancing the operating speed of the semiconductor integrated circuit. However, as the frequency of the clock increases, noise is apt to occur within each clock driver. Therefore, the noise propagated from the clock drivers to the logic circuits or the like has conventionally resulted in one cause of interference with the speeding up of the semiconductor integrated circuit.
Besides, the conventional semiconductor integrated circuit is also accompanied by a drawback that when the clock frequency is made high to increase the operating speed, power consumption of each clock driver increases.